View ATTINY2313V-8MU_3748957.PDF datasheet online --- IC-ON-LINE

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1 2543c?avr?12/03 features utilizes the avr ? risc architecture avr ? high-performance and low-power risc architecture ? 120 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation data and non-volatile program and data memories ? 2k bytes of in-system self programmable flash endurance 10,000 write/erase cycles ? 128 bytes in-system programmable eeprom endurance: 100,000 write/erase cycles ? 128 bytes internal sram ? programming lock for flash program and eeprom data security peripheral features ? one 8-bit timer/counter with separate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare and capture modes ? four pwm channels ? on-chip analog comparator ? programmable watchdog timer with on-chip oscillator ? usi ? universal serial interface ? full duplex usart special microcontroller features ? debugwire on-chip debugging ? in-system programmable via spi port ? external and internal interrupt sources ? low-power idle, power-down, and standby modes ? enhanced power-on reset circuit ? programmable brown-out detection circuit ? internal calibrated oscillator i/o and packages ? 18 programmable i/o lines ? 20-pin pdip, 20-pin soic, and 32-pin mlf operating voltages ? 1.8 - 5.5v (attiny2313) speed grades ? attiny2313v: 0 - 2 mhz @ 1.8 - 5.5v, 0 - 8 mhz @ 2.4 - 5.5v ? attiny2313: 0 - 8 mhz @ 2.7 - 5.5v, 0 - 16 mhz @ 4.5 - 5.5v power consumption estimates ? active mode 1 mhz, 1.8v: 300 a 32 khz, 1.8v: 20 a (including oscillator) ? power-down mode < 0.2 a at 1.8v 8-bit microcontroller with 2k bytes in-system programmable flash attiny2313/v preliminary summary rev. 2543c?avr?12/03
2 attiny2313/v 2543c?avr?12/03 pin configurations figure 1. pinout attiny2313 (reset/dw)pa2 (rxd)pd0 (txd)pd1 (xtal2)pa1 (xtal1)pa0 (ckout/xck/int0)pd2 (int1)pd3 (t0)pd4 (oc0b/t1)pd5 gnd 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 vcc pb7(ucsk/sck/pcint7) pb6(do/pcint6) pb5(di/sda/pcint5) pb4(oc1b/pcint4) pb3(oc1a/pcint3) pb2(oc0a/pcint2) pb1(ain1/pcint1) pb0(ain0/pcint0) pd6(icp) mlf top view pdip/soic note: bottom pad should be soldered to ground. 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 nc (xtal2)pa1 (xtal1)pa0 nc nc (ckout/xck/int0)pd2 nc nc nc pb4(oc1b/pcint4) nc nc nc pb3(oc1a/pcint3) pb2(oc0a/pcint2) nc (int1)pd3 (t0)pd4 (oc0b/t1)pd5 gnd (icp)pd6 (ain0/pcint0)pb0 (ain1/pcint1)pb1 nc pd1(txd) pd0(rxd) pa2(reset/dw) vcc pb7(ucsk/sck/pcint7) pb6(do/pcint6) pb5(di/sda/pcint5) nc
3 attiny2313/v 2543c?avr?12/03 overview the attiny2313 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the attiny2313 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. block diagram figure 2. block diagram program counter program flash instruction register gnd vcc instruction decoder control lines stack pointer sram general purpose register alu status register programming logic spi 8-bit data bus xtal1 xtal2 reset internal oscillator oscillator watchdog timer timing and control mcu control register mcu status register timer/ counters interrupt unit eeprom usi usart analog comparator data register portb data dir. reg. portb data register porta data dir. reg. porta portb drivers pb0 - pb7 porta drivers pa 0 - pa 2 data register portd data dir. reg. portd portd drivers pd0 - pd6 on-chip debugger internal calibrated oscillator
4 attiny2313/v 2543c?avr?12/03 the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the attiny2313 provides the following features: 2k bytes of in-system programmable flash, 128 bytes eeprom, 128 bytes sram, 18 general purpose i/o lines, 32 general purpose working registers, a single-wire interface for on-chip debugging, two flexible timer/counters with compare modes, internal and external interrupts, a serial program- mable usart, universal serial interface with start condition detector, a programmable watchdog timer with internal osc illator, and three software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, and interrupt system to continue functioning. the power-down mode saves the register con- tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. this allows very fast start-up combined with low-power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, or by a conventional non-volatile memory programmer. by combining an 8-bit risc cpu with in-system self-programmable flash on a mono- lithic chip, the atmel attiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the attiny2313 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-cir- cuit emulators, and evaluation kits.
5 attiny2313/v 2543c?avr?12/03 pin descriptions vcc digital supply voltage. gnd ground. port a (pa2..pa0) port a is a 3-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the attiny2313 as listed on page 53. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the attiny2313 as listed on page 53. port d (pd6..pd0) port d is a 7-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pins that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the attiny2313 as listed on page 56. reset reset input. a low level on this pin for longer than the minimum pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 15 on page 34. shorter pulses are not guaranteed to generate a reset. the reset input is an alternate function for pa2 and dw. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal1 is an alternate function for pa0. xtal2 output from the inverting oscillator amplifier. xtal2 is an alternate function for pa1.
6 attiny2313/v 2543c?avr?12/03 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 0x3f (0x5f) sreg i t h s v n z c 8 0x3e (0x5e) reserved ? ? ? ? ? ? ? ? 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 10 0x3c (0x5c) ocr0b timer/counter0 ? compare register b 78 0x3b (0x5b) gimsk int1 int0 pcie ? ? ? ? ?61 0x3a (0x5a) eifr intf1 intf0 pcif ? ? ? ? ?62 0x39 (0x59) timsk toie1 ocie1a ocie1b ? icie1 ocie0b toie0 ocie0a 79, 110 0x38 (0x58) tifr tov1 ocf1a ocf1b ? icf1 ocf0b tov0 ocf0a 79 0x37 (0x57) spmcsr ? ? ? ctpb rflb pgwrt pgers spmen 156 0x36 (0x56) ocr0a timer/counter0 ? compare register a 78 0x35 (0x55) mcucr pud sm1 se sm0 isc11 isc10 isc01 isc00 53 0x34 (0x54) mcusr ? ? ? ? wdrfborfextrf porf 37 0x33 (0x53) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 77 0x32 (0x52) tcnt0 timer/counter0 (8-bit) 78 0x31 (0x51) osccal ? cal6 cal5 cal4 cal3 cal2 cal1 cal0 26 0x30 (0x50) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 74 0x2f (0x4f) tccr1a com1a1 com1a0 com1b1 com1bo ? ?wgm11wgm10 105 0x2e (0x4e) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 108 0x2d (0x4d) tcnt1h timer/counter1 ? counter register high byte 109 0x2c (0x4c) tcnt1l timer/counter1 ? counter register low byte 109 0x2b (0x4b) ocr1ah timer/counter1 ? compare register a high byte 109 0x2a (0x4a) ocr1al timer/counter1 ? compare register a low byte 109 0x29 (0x49) ocr1bh timer/counter1 ? compare register b high byte 110 0x28 (0x48) ocr1bl timer/counter1 ? compare register b low byte 110 0x27 (0x47) reserved ? ? ? ? ? ? ? ? 0x26 (0x46) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 28 0x25 (0x45) icr1h timer/counter1 - input capture register high byte 110 0x24 (0x44) icr1l timer/counter1 - input capture register low byte 110 0x23 (0x43) gtccr ? ? ? ? ? ? ? psr10 82 0x22 (ox42) tccr1c foc1a foc1b ? ? ? ? ? ?109 0x21 (0x41) wdtcr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 39 0x20 (0x40) pcmsk pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 62 0x1f (0x3f) reserved ? ? ? ? ? ? ? ? 0x1e (0x3e) eear ? eeprom address register 17 0x1d (0x3d) eedr eeprom data register 17 0x1c (0x3c) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 17 0x1b (0x3b) porta ? ? ? ? ? portr2 porta1 porta0 59 0x1a (0x3a) ddra ? ? ? ? ? dda2 dda1 dda0 59 0x19 (0x39) pina ? ? ? ? ? pina2 pina1 pina0 59 0x18 (0x38) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 59 0x17 (0x37) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 59 0x16 (0x36) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 59 0x15 (0x35) gpior2 general purpose i/o register 2 21 0x14 (0x34) gpior1 general purpose i/o register 1 21 0x13 (0x33) gpior0 general purpose i/o register 0 21 0x12 (0x32) portd ? portd6 portd5 portd4 portd3 portd2 portd1 portd0 59 0x11 (0x31) ddrd ? ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 59 0x10 (0x30) pind ? pind6 pind5 pind4 pind3 pind2 pind1 pind0 59 0x0f (0x2f) usidr usi data register 145 0x0e (0x2e) usisr usisif usioif usipf usidc usicnt3 usicnt2 usicnt1 usicnt0 146 0x0d (0x2d) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 147 0x0c (0x2c) udr uart data register (8-bit) 130 0x0b (0x2b) ucsra rxc txc udre fe dor upe u2x mpcm 130 0x0a (0x2a) ucsrb rxcie txcie udrie rxen txen ucsz2 rxb8 txb8 132 0x09 (0x29) ubrrl ubrrh[7:0] 134 0x08 (0x28) acsr acd acbg aco aci acie acic acis1 acis0 150 0x07 (0x27) reserved ? ? ? ? ? ? ? ? 0x06 (0x26) reserved ? ? ? ? ? ? ? ? 0x05 (0x25) reserved ? ? ? ? ? ? ? ? 0x04 (0x24) reserved ? ? ? ? ? ? ? ? 0x03 (0x23) ucsrc ? umsel upm1 upm0 usbs ucsz1 ucsz0 ucpol 133 0x02 (0x22) ubrrh ? ? ? ? ubrrh[11:8] 134 0x01 (0x21) didr ? ? ? ? ? ? ain1d ain0d 151 0x00 (0x20) reserved ? ? ? ? ? ? ? ?
7 attiny2313/v 2543c?avr?12/03 note: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specified bit, and can theref ore be used on registers containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses.
8 attiny2313/v 2543c?avr?12/03 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? kz,n,v1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1
9 attiny2313/v 2543c?avr?12/03 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
10 attiny2313/v 2543c?avr?12/03 ordering information note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging alternative. 3. see figure 81 on page 179 and figure 82 on page 179. speed (mhz) power supply ordering code package (1) operation range 8 (3) 1.8 - 5.5v attiny2313v-8pi attiny2313v-8si attiny2313v-8mi attiny2313v-8pj (2) attiny2313v-8sj (2) attiny2313v-8mj (2) 20p3 20s 32m1-a 20p3 20s 32m1-a industrial (-4 0 c to 85 c) 16 (3) 2.7 - 5.5v attiny2313-16pi attiny2313-16si attiny2313-16mi attiny2313-16pj (2) attiny2313-16sj (2) attiny2313-16mj (2) 20p3 20s 32m1-a 20p3 20s 32m1-a industrial (-4 0 c to 85 c) package type 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s 20-lead, 0.300" wide, plastic gull wing small outline (soic) 32m1-a 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm, micro lead frame package (mlf)
11 attiny2313/v 2543c?avr?12/03 packaging information 20p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20p3 , 20-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 20p3 09/28/01 pin 1 e1 a1 b e b1 c l seating plane a d e eb ec common dimensions (unit of measure = mm) symbol min nom max note a ? ? 5.334 a1 0.381 ? ? d 25.984 ? 25.493 note 2 e 7.620 ? 8.255 e1 6.096 ? 7.112 note 2 b 0.356 ? 0.559 b1 1.270 ? 1.551 l 2.921 ? 3.810 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001, variation ad. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
12 attiny2313/v 2543c?avr?12/03 20s 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20s2 , 20-lead, 0.300" wide body, plastic gull wing small outline package (soic) 1/9/02 20s2 a l a1 end view side view top view h e b n 1 e a d c common dimensions (unit of measure = inches) symbol min nom max note notes: 1. this drawing is for general information only; refer to jedec drawing ms-013, variation ac for additional information. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exc eed 0.15 mm (0.006") per side. 3. dimension "e" does not include inter-lead flash or protrusion. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "l" is the length of the terminal for soldering to a substrate. 5. the lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. a 0.0926 0.1043 a1 0.0040 0.0118 b 0.0130 0.0200 4 c 0.0091 0.0125 d 0.4961 0.5118 1 e 0.2914 0.2992 2 h 0.3940 0.4190 l 0.0160 0.050 3 e 0.050 bsc
13 attiny2313/v 2543c?avr?12/03 32m1-a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32m1-a , 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm micro lead frame package (mlf) c 32m1-a 01/15/03 common dimensions (unit of measure = mm) symbol min nom max note pin 1 id d1 d e1 e e b a3 a2 a1 a d2 e2 0.08 c l 1 2 3 p p 0 1 2 3 a 0.80 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a3 0.20 ref b 0.18 0.23 0.30 d 5.00 bsc d1 4.75 bsc d2 2.95 3.10 3.25 e 5.00 bsc e1 4.75bsc e2 2.95 3.10 3.25 e 0.50 bsc l 0.30 0.40 0.50 p ? ? 0.60 ? ? 12 o notes: 1. jedec standard mo-220, fig. 2 (anvil singulation), vhhd-2. top view side view bottom view 0 pin 1 id
14 attiny2313/v 2543c?avr?12/03 errata the revision in this section refers to the revision of the attiny2313 device. attiny2313 rev a wrong values read after erase only operation parallel programming does not work 1. wrong values read after erase only operation at supply voltages below 2.7 v, an eeprom location that is erased by the erase only operation may read as programmed (0x00). problem fix/workaround if it is necessary to read an eeprom location after erase only, use an atomic write operation with 0xff as data in order to erase a location. in any case, the write only operation can be used as intended. thus no special considerations are needed as long as the erased location is not read before it is programmed. 2. parallel programming does not work parallel programming is not functioning correctly. because of this, reprogramming of the device is impossible if one of the following modes are selected: ? in-system programming disabled (spien unprogrammed) ? reset disabled (rstdisbl programmed) problem fix/workaround serial programming is still working correctly. by avoiding the two modes above, the device can be reprogrammed.
15 attiny2313/v 2543c?avr?12/03 datasheet change log for attiny2313 please note that the referring page numbers in this section are referred to this docu- ment. the referring revision in this section are referring to the document revision. changes from rev. 2514b-09/03 to rev. 2514c-12/03 1. updated ?calibrated internal rc oscillator? on page 25. changes from rev. 2514a-09/03 to rev. 2514b-09/03 1. fixed typo from uart to usart and updated speed grades and power con- sumption estimates in ?features? on page 1. 2. updated ?pin configurations? on page 2. 3. updated table 15 on page 34 and table 81 on page 178. 4. updated item 5 in ?serial programming algorithm? on page 173. 5. updated ?electrical characteristics? on page 177. 6. updated figure 81 on page 179 and added figure 82 on page 179. 7. changed sfior to gtccr in ?register summary? on page 6. 8. updated ?ordering information? on page 10. 9. added new errata in ?errata? on page 14.
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